1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming ruthenium conductive structures in a metallization layer.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reducing the physical size (feature sizes) of circuit elements, such as transistors. Field effect transistors (FETs) come in a variety of configurations, e.g., planar transistor devices, FinFET devices, nanowire devices, etc. Irrespective of the form of the FET, they have a gate electrode, a source region, a drain region and a channel region positioned between the source and drain regions. The state of the field effect transistor (“ON” or “OFF”) is controlled by the gate electrode. Upon the application of an appropriate control voltage to the gate electrode, the channel region becomes conductive, thereby allowing current to flow between the source and drain regions.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years, particularly the channel length of transistor devices. As a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level where the actual semiconductor-based circuit elements, such as transistors, are formed in and above the semiconductor substrate.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections or “wiring arrangement” for the individual circuit elements cannot be established within the same device level where the circuit elements are manufactured. Accordingly, the various electrical connections that constitute the overall wiring pattern for the integrated circuit product are formed in one or more additional so-called “metallization layers” that are formed or stacked above the device level of the product. A typical integrated circuit product may contain several of such metallization layers, e.g., 7-12, depending upon the complexity of the integrated circuit product.
Each of these metallization layers is typically comprised of a layer of insulating material with conductive metal lines and/or conductive vias formed in the layer of material. Generally, the conductive lines provide the intra-level (i.e., within layer) electrical connections, while the conductive vias provide the inter-level connections or vertical connections between different metallization layers or levels. These conductive lines and conductive vias may be comprised of a variety of different materials, e.g., copper, with appropriate barrier layers, etc. The first metallization layer in an integrated circuit product is typically referred to as the “M1” layer, while the conductive vias that are used to establish electrical connection between the M1 layer and lower level conductive structures that physically contact the devices are typically referred to as “V0” vias. For current advanced integrated circuit products, the conductive lines and conductive vias in these metallization layers are typically comprised of copper, and they are formed in layers of insulating material using known damascene or dual-damascene techniques. As noted above, additional metallization layers are formed above the M1 layer, e.g., M2/V1, M3/V2, etc. Within the industry, conductive structures below the V0 level are generally considered to be “device-level” contacts or simply “contacts,” as they contact the “device” (e.g., a transistor) that is formed in the silicon substrate.
However, with each advancing generation of products, the critical dimension of the conductive structures, e.g., the lateral width of a conductive line, tends to decrease as well. Filling relatively small trenches in a layer of insulating material with copper material, using electroplating or electroless plating techniques, can be difficult. Moreover, even though the overall critical dimension of these conductive structures decreases, the thickness of the barrier layer(s) that must be formed in these trenches remains about the same, i.e., the barrier layer thickness does not scale down (at least not significantly) as the overall critical dimension (lateral width) of the conductive structure, e.g., a conductive line, is reduced. Accordingly, there is less space within the trench for the more conductive copper material, i.e., the bulk metal of the conductive structure, and, in a relative sense, the current density within such smaller conductive structures increases during operation. In turn, this increase in current density of the bulk copper material can lead to more undesirable electromigration of the copper material during operation of the IC product, which can reduce product performance and/or lead to product failure.
Investigations have been made with regard to using alternative materials, e.g., cobalt, ruthenium, etc., to replace copper as the bulk portion of the conductive structures. FIGS. 1A-1B depict one illustrative prior art method of forming conductive structures in a metallization layer on an integrated circuit product using such alternative materials. FIG. 1A is a simplified view of an illustrative metallization layer of a prior art integrated circuit product 10. At this point in the fabrication process, the product 10 comprises illustrative metallization layers 11 and 13. The metallization layers 11, 13 are typically formed during so-called BEOL (Back-End-Of-Line) processing operations. The metallization layer 11 comprises a layer of insulating material 12, a plurality of conductive structures 14, e.g., positioned in trenches 15 formed in the layer of insulating material 12, and an etch stop or cap layer 16. The metallization layer 13 comprises a layer of insulating material 18, a conductive structure 21 comprised of a conductive material 20 and one or more barrier/adhesion layers 22. The layers 12 and 18 may be comprised of a variety of different materials, e.g., a low-k material (k value of 3.3 or less), silicon dioxide, etc., and they may be formed to any desired thickness. The etch stop/cap layer 16 may be comprised of any of a variety of materials such as silicon nitride, silicon oxynitride, etc., and it may be formed to any desired thickness. The conductive structures 14 may be comprised of a variety of different materials e.g., copper, tungsten, cobalt, etc. The conductive structure 21 may be comprised of a conductive material 20 such as ruthenium or cobalt. The barrier/adhesion layer 22 may be comprised of one or more layers of various materials, such as titanium, titanium nitride, tantalum, tantalum nitride, etc. The material(s) selected for such barrier/adhesion layer(s) 22 may be based upon the material selected for the bulk metal material 20.
The conductive structure 21 may be formed by performing one or more etching processes to define an opening 18A in the layer of insulating material 18 and a plurality of openings 16A in the etch stop/cap layer 16. Each of the openings 16A exposes an upper surface of one of the conductive structures 14. Thereafter, the product was placed in a processing chamber and subject to an oxide cleaning process so as to remove any oxide materials (not shown), e.g., copper oxide, tungsten oxide, that may have been formed on the upper surfaces of the exposed conductive structures 14. Then, a deposition process was performed to deposit the barrier layer(s) 22 in the openings 16A, 18A and above the exposed conductive structures 14. Next, the conductive material 20 was formed on the product and a CMP process was performed so as to result in the final conductive structure 21.
FIG. 1B is an enlarged view of the portion of the conductive structure 21 depicted in the dashed-line region 24 in FIG. 1A. Unfortunately, using this prior art process flow, it may be the case that an interfacial oxide layer 26, e.g., copper oxide, tungsten oxide, etc., will be formed on or above the upper surface of the conductive structure 14. In the depicted example, the interfacial oxide layer 26 covers substantially the entire upper surface of the conductive structure 14, however, that may not be the case in all situations. The presence of the interfacial oxide layer 26 causes the electrical resistance of the overall wiring structure to increase, which can lead to a reduction in device performance.
The present disclosure is directed to various methods of forming ruthenium conductive structures in a metallization layer that may solve or at least reduce some of the problems identified above.